//-- //////////////////////////////////////////////////////////////////////////////
//-- /// Copyright (c) 2013, Jahanzeb Ahmad
//-- /// All rights reserved.
//-- ///
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//-- /// are permitted provided that the following conditions are met:
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//-- ///    this list of conditions and the following disclaimer.
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//-- ///    other materials provided with the distribution.
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//-- //////////////////////////////////////////////////////////////////////////////

module HeaderRam(d, waddr, raddr, we, clk, q);
output [7:0] q;
input [7:0] d;
input[9:0] raddr;
input[9:0] waddr;
input clk, we;

reg [9:0] read_addr;
reg[7:0] mem [1023:0] /* synthesis syn_ramstyle="block_ram" */;

initial $readmemh("header.hex", mem);

assign q = mem[read_addr];

always @(posedge clk) begin
if (we)
mem[waddr] <= d;
read_addr <= raddr;
end

endmodule
